Buck-boost power converters can convert an input voltage into an output voltage higher than, equal to or lower than the input voltage and can generally be operated with wide input voltage range. Therefore, buck-boost power converters are widely used in power management applications.
FIG. 1 illustrates a topology 10 of the power switches of a conventional buck-boost power converter. The topology 10 comprises a first power switch SWA, a second power switch SWB, a third power switch SWC and a fourth power switch SWD. The first power switch SWA and the second power switch SWB are coupled in series between an input port IN and a reference ground GND, and have a common connection SW1 referred to as a first switching node SW1. The third power switch SWC and the fourth power switch SWD are coupled in series between an output port OUT and the reference ground GND, and have a common connection SW2 referred to as a second switching node SW2. An inductor L is coupled between the first switching node SW1 and the second switching node SW2. The buck-boost power converter typically further comprises a control circuit to provide driving signals DR1, DR2, DR3 and DR4 respectively to the control terminals GA, GB, GC and GD of the power switches SWA, SWB, SWC and SWD to control the on and off switching of the power switches SWA, SWB, SWC and SWD so as to converter an input voltage Vin at the input port IN to an appropriate output voltage Vo at the output port OUT.
The control circuit typically comprises drivers to respectively drive the power switches SWA, SWB, SWC and SWD. For instance, a driver DRA to drive the first power switch SWA and a driver DRD to drive the fourth power switch SWD are illustrated in FIG. 1. If the first power switch SWA and the fourth power switch SWD are N channel power switching devices (e.g. N channel field effect transistors, N channel double diffused metal oxide semiconductor transistors etc.), bootstrap circuits should be provided to enhance the driving capability of the drivers DRA and DRD. For example, in FIG. 1, a first bootstrap capacitor CB1 coupled between a first bootstrap terminal BST1 and the first switching node SW1 and a second bootstrap capacitor CB2 coupled between a second bootstrap terminal BST2 and the second switching node SW2 are shown. The first bootstrap capacitor CB1 and the second bootstrap capacitor CB2 are respectively configured to generate a first bootstrap voltage VBST1 referenced with the voltage at the first switching node SW1 and a second bootstrap voltage VBST2 referenced with the voltage at the second switching node SW2. The first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 are respectively used to enhance the driving capability of the driving signals DR1 and DR4 output from the drivers DRA and DRD to fully turn the first power switch SWA and the fourth power switch SWD on/off.
The first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 can be respectively generated through charging the first bootstrap capacitor CB1 and the second bootstrap capacitor CB2. However, under certain operation conditions, such as when the buck-boost power converter operates under light load or no-load condition, charges on the first bootstrap capacitor CB1 and the second bootstrap capacitor CB2 may not be enough, leading to decrease in the first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 to the extent that may not be able to drive the first power switch SWA and the fourth power switch SWD to switch on/off normally. Therefore, when the first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 is lower than a predetermined threshold, the first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 should be refreshed i.e. the first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 should be charged (e.g. through charging the first bootstrap capacitor CB1 and the second bootstrap capacitor CB2) to recover to a desired bootstrap voltage value.
In pulse skipping mode, when an inductor current IL flowing through the inductor L crosses zero, the power switches SWA, SWB, SWC and SWD are typically all switched off. For this situation, the voltage at the first switching node SW1 and the voltage at the second switching node SW2 will be oscillating or floating e.g. at a high potential as the input voltage Vin or a low potential as the reference ground GND. If the first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 just happen needing to be refreshed in this situation, for instance be refreshed with the bootstrap refresh scheme taught in patent ZL201210315162.5, the voltage at the first switching node SW1 and the voltage at the second switching node SW2 will oscillate at a high frequency, leading to failure in refreshing the first bootstrap voltage VBST1 and the second bootstrap voltage VBST2 and disturbance in the output voltage Vo of the buck-boost power converter. FIG. 2 illustrates a waveform diagram showing simulation waveforms of the output voltage Vo, the inductor current IL, the voltage VSW1 at the first switching node SW1 and the voltage VSW2 at the second switching node SW2 when refreshing the bootstrap voltages VBST1 and VBST2 in the pulse skipping mode under the circumstance when the inductor current IL crosses zero and the power switches SWA, SWB, SWC and SWD are all switched off. It can be seen from FIG. 2 that under this circumstance, oscillation occurs in the voltage at the first switching node SW1 and in the voltage at the second switching node SW2, leading to disturbance in the output voltage Vo of the buck-boost power converter.